EDN: Why NoC tiling matters in AI-centric SoC designs

At a time when artificial intelligence (AI)-centric system-on-chips (SoCs) are growing in size and complexity, network-on-chip (NoC) tiling hand in hand with mesh topology can support faster development of compute chip designs.

That's the premise around which Arteris has launched tiling as the next evolutionary step in its NoC IP offerings to facilitate scaling, condense design time, speed testing, and reduce design risk. The Campbell, California-based supplier of IPs is combining NoC tiling with mesh topologies for SoC designs catering to larger AI data volumes and complex algorithms.

Figure 1 Mesh topologies complement NoC tiling to further reduce the overall SoC connectivity execution time by up to 50% versus manually integrated, non-tiled designs.

SiMa.ai, a developer of machine learning (ML) SoCs, has created an Arm-based, multi-modal, software-centric edge AI platform using this mesh-based NoC IP. The upstart's AI chip models range from CNNs to multi-modal GenAI and everything in between with scalable performance per watt.

But before we delve into further details about this new NoC technology for SoC designs, below is a brief recap of what it's all about and why it has been launched now.

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