New fractional gates reduce circuit depth for utility-scale workloadsQuantum EnablementQuantum Software Updates

IBM® is introducing a new type of quantum logic gate to IBM Quantum Heron™ QPUs. They're called "fractional gates," and they are a powerful new tool for reducing the circuit depth of quantum workloads. Fractional gates introduce helpful new efficiencies for building utility-scale quantum experiments, and this is particularly true of quantum experiments designed to simulate nature. So, how do they work?

When running large experiments with 100+ qubits and thousands of gates, it's important to take advantage of any opportunity to reduce the depth of your quantum circuits. Shorter circuits allow us to do more with the noisy quantum hardware we have today. Fractional gates help to reduce circuit depths by adding two useful new ISA instructions to our quantum fleet.

These new ISA instructions give you the ability to execute a single- or two-qubit rotation in the form of either an RX(θ)R_X(\theta)gate or an RZZ(θ)R_{ZZ}(\theta)gate. You can use these gates to significantly reduce gate counts in just about any quantum circuits containing single- and two-qubit rotations - such as, for example, the quantum circuits we use to simulate the dynamics of quantum systems.

An important note on pulse-level control for IBM Quantum QPUs

Please note that alongside the rollout of fractional gates, we are also deprecating support for pulse-level control on all IBM Quantum QPUs.

Pulse-level control will be removed from the service on February 3, 2025. This decision is part of our ongoing efforts to focus more of our attention and resources on higher-level services aimed at supporting utility-scale experiments and the search for quantum advantage.

If you are someone who has been using IBM Quantum's pulse-level control features for optimal control studies, we encourage you to explore tools and resources like Qiskit Dynamics that enable such studies in simulation and may provide a replacement for your specific use case.

We mention this deprecation here because one of the most common use cases for pulse-level control is the direct implementation of the single- and two-qubit rotations described in the introduction to this article. As we'll see below, the new fractional gates provide a convenient replacement for that functionality.

Why are traditional RX(θ)R_X(\theta)and RZZ(θ)R_{ZZ}(\theta)gates less efficient?

To give you an idea of the computational cost-savings fractional gates can bring to your final circuit depth, let's look at how the Qiskit transpiler typically decomposes an RX(θ)R_X(\theta)and RZZ(θ)R_{ZZ}(\theta)gate. We'll start by first creating two circuits, one with an RX(θ)R_X(\theta)gate and one with an RZZ(θ)R_{ZZ}(\theta)gate. Here's the RX(θ)R_X(\theta)gate:

And here's the RZZ(θ)R_{ZZ}(\theta)gate:

Then, when we transpile them, the RX(θ)R_X(\theta)gate becomes:

This is a substantial increase in gate depth. The circuit has quintupled in size from just a single quantum logic gate to five.

In this case, it's worth noting that only the X\sqrt{X}gates contribute to the gate error. This is due to the specific way we execute the RZRZgate in the IBM Quantum fleet. Still, even if we only look at the X\sqrt{X}gates, that's double the original gate depth, and that doubling becomes significant when we extrapolate to a circuit comprising 100+ qubits.

Let's now take a look at how the RZZ(θ)R_ZZ(\theta)gate is decomposed:

That's an even larger increase! To execute an RZZ(θ)R_ZZ(\theta)gate, we need to execute twoCZCZgates, which perform the action of a CNOT gate, along with several more single-qubit gates.

However, using the new fractional gates, we can execute these single and two-qubit rotations directly and avoid this issue of increasing circuit depth.

How to use fractional gates: A simple example based on the Ising model

To quickly demonstrate how to use the new fractional gate instructions, let's look at an example circuit that simulates the dynamics of a transverse field Ising model. This is a relatively simple quantum system to simulate and will serve as a useful case study demonstrating the power of fractional gates.

In this model, each qubit represents a single site in either a one-dimensional line or a two-dimensional lattice. For this example, let's simulate the time evolution of a one-dimensional chain of sites. We can construct the circuit in the following way:

Now, to take advantage of fractional gates, all we have to do is specify a backend that supports them! The transpiler will know what to do from there:

To see the difference this makes, let's now compare the scheduled circuit time we get using a backend with fractional gates enabled vs. one that doesn't have fractional gates enabled. Here's what we get using fractional gates:

And here's what we get without fractional gates-as you can see, system cycle time is more than doubled:

Fractional gates limitations

Fractional gates are a powerful tool, but they do come with a few limitations that you should keep in mind. For one thing, you cannot use fractional gates with every backend. You can use the following code to query which backends support them:

Alternatively, you can use something like the following to query which backends support fractional gates:

This second code example does the same thing as the first example, but keeps the details under the cover. The same can be passed to .

Another consideration is that, at least for now, you will not be able to use fractional gates in combination with dynamic circuits in the same job, and you cannot use them with primitive-based error mitigation methods like PEC, ZNE with PEA, or Pauli twirling. You will, however, be able to use fractional gates alongside dynamical decoupling and the T-REx method. In the future, we may be able to relax the current limitations.

You'll find a helpful chart outlining which error mitigations you can and cannot use with fractional gates in our documentation.

Getting started with fractional gates

We hope you'll experiment with the new fractional gates to see how they can help you reduce gate depth for your utility-scale workloads. For more guidance on how to use-and how not to use-fractional gates, be sure to check our documentation here.

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